Formal Methods in Computer-Aided Design
Formal Methods in Computer-Aided Design: Third International Conference, FMCAD 2000 Austin, TX, USA, November 1–3, 2000 ProceedingsAuthor: Warren A. Hunt Jr., Steven D. Johnson Published by Springer Berlin Heidelberg ISBN: 978-3-540-41219-9 DOI: 10.1007/3-540-40922-XTable of Contents:Applications of Hierarchical Verification in Model Checking
Trends in Computing
A Case Study in Formal Verification of Register-Transfer Logic with ACL2: The Floating Point Adder of the AMD Athlon
An Algorithm for Strongly Connected Component Analysis in n log n Symbolic Steps
Automated Refinement Checking for Asynchronous Processes
Border-Block Triangular Form and Conjunction Schedule in Image Computation
B2M: A Semantic Based Tool for BLIF Hardware Descriptions
Checking Safety Properties Using Induction and a SAT-Solver
Combining Stream-Based and State-Based Verification Techniques
A Comparative Study of Symbolic Algorithms for the Computation of Fair Cycles
Correctness of Pipelined Machines
Do You Trust Your Model Checker?
Executable Protocol Specification in ESL
Formal Verification of Floating Point Trigonometric Functions
Hardware Modeling Using Function Encapsulation
A Methodology for the Formal Analysis of Asynchronous Micropipelines
A Methodology for Large-Scale Hardware Verification
Model Checking Synchronous Timing Diagrams
Model Reductions and a Case Study
Modeling and Parameters Synthesis for an Air TrafficManagement System
Trends in Computing
A Case Study in Formal Verification of Register-Transfer Logic with ACL2: The Floating Point Adder of the AMD Athlon
An Algorithm for Strongly Connected Component Analysis in n log n Symbolic Steps
Automated Refinement Checking for Asynchronous Processes
Border-Block Triangular Form and Conjunction Schedule in Image Computation
B2M: A Semantic Based Tool for BLIF Hardware Descriptions
Checking Safety Properties Using Induction and a SAT-Solver
Combining Stream-Based and State-Based Verification Techniques
A Comparative Study of Symbolic Algorithms for the Computation of Fair Cycles
Correctness of Pipelined Machines
Do You Trust Your Model Checker?
Executable Protocol Specification in ESL
Formal Verification of Floating Point Trigonometric Functions
Hardware Modeling Using Function Encapsulation
A Methodology for the Formal Analysis of Asynchronous Micropipelines
A Methodology for Large-Scale Hardware Verification
Model Checking Synchronous Timing Diagrams
Model Reductions and a Case Study
Modeling and Parameters Synthesis for an Air TrafficManagement System
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